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Sheet目录3881

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2004 Microchip Technology Inc.

DS30491C-page 233

PIC18F6585/8585/6680/8680

18.1

USART Baud Rate Generator (BRG)

The BRG is a dedicated 8-bit or 16-bit generator that

supports both the Asynchronous and Synchronous

modes of the USART. By default, the BRG operates in

8-bit mode; setting the BRG16 bit (BAUDCON<3>)

selects 16-bit mode.

The SPBRGH:SPBRG register pair controls the period

of a free-running timer. In Asynchronous mode, bits

BRGH (TXSTA<2>) and BRG16 also control the baud

rate. In Synchronous mode, bit BRGH is ignored.

Table 18-1 shows the formula for computation of the

baud rate for different USART modes which only apply

in Master mode (internally generated clock).

Given the desired baud rate and FOSC, the nearest

integer value for the SPBRGH:SPBRG registers can be

calculated using the formulas in Table 18-1. From this,

the error in baud rate can be determined. An example

calculation is shown in Example 18-1. Typical baud

rates and error values for the various Asynchronous

modes are shown in Table 18-2. It may be advantageous

to use the high baud rate (BRGH = 1) or the 16-bit BRG

to reduce the baud rate error, or achieve a slow baud

rate for a fast oscillator frequency.

Writing a new value to the SPBRGH:SPBRG registers

causes the BRG timer to be reset (or cleared). This

ensures the BRG does not wait for a timer overflow

before outputting the new baud rate.

18.1.1

SAMPLING

The data on the RC7/RX/DT pin is sampled three times

by a majority detect circuit to determine if a high or a

low level is present at the RX pin.

TABLE 18-1:

BAUD RATE FORMULAS

EXAMPLE 18-1:

CALCULATING BAUD RATE ERROR

TABLE 18-2:

REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR

Configuration Bits

BRG/USART Mode

Baud Rate Formula

SYNC

BRG16

BRGH

8-bit/Asynchronous

FOSC/[64 (n + 1)]

8-bit/Asynchronous

FOSC/[16 (n + 1)]

16-bit/Asynchronous

FOSC/[4 (n + 1)]

8-bit/Synchronous

16-bit/Synchronous

Legend: x = Don’t care, n = Value of SPBRGH:SPBRG register pair

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on all

other Resets

TXSTA

CSRC

TX9

TXEN

SYNC

SENDB

BRGH

TRMT

TX9D

0000 0010

RCSTA

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

0000 000x

BAUDCON

—

RCIDL

—

SCKP

BRG16

—

WUE

ABDEN

-1-0 0-00

SPBRGH

Baud Rate Generator Register, High Byte

0000 0000

SPBRG

Baud Rate Generator Register, Low Byte

0000 0000

Legend:

= unknown, - = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.

For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:

Desired Baud Rate

= FOSC/(64 ([SPBRGH:SPBRG] + 1))

Solving for SPBRGH:SPBRG:

X= ((FOSC/Desired Baud Rate)/64) – 1

= ((16000000/9600)/64) – 1

= [25.042] = 25

Calculated Baud Rate= 16000000/(64 (25 + 1))

= 9615

Error

= (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate

= (9615 – 9600)/9600 = 0.16%

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